The present invention generally relates to a semiconductor device comprising transistors and to a method of manufacturing the semiconductor device. The present invention has particular applicability in manufacturing a high density Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Over the last few decades, the electronics industry has undergone a revolutionary decrease in the size of device elements formed in integrated circuits (IC). Efforts have contributed to increasing the density of circuit elements and device performance. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Currently, the most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped conductor having uniform conductivity. An input signal is typically applied to the gate electrode via a gate terminal. Heavily doped active regions, e.g., source/drain regions, are formed in the semiconductor substrate and are connected to source/drain terminals. The typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether an active region acts as a source or drain depends on the respective applied voltages and the type of device being made, e.g., PMOS or NMOS. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The channel region is typically lightly doped with an impurity type opposite to that of the source/drain regions, and the impurity concentration profile is substantially uniform from the surface into the substrate, as shown by line A in FIG. 2. The gate electrode is generally separated from the semiconductor substrate by an insulating layer, e.g., an oxide layer, to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
In conventional manufacturing technologies, a channel implantation process is frequently performed to augment the substrate doping of the same conductivity. Thus, for an NMOS device, a p-type impurity is ion implanted into the substrate and channel region, and for a PMOS device, an n-type impurity is ion implanted into the substrate and channel region. The purpose of this channel implant is typically to adjust a threshold voltage and limit xe2x80x9cpunch-throughxe2x80x9d. The threshold voltage is the minimum required voltage applied to the gate electrode of a MOSFET device so as to invert the conductivity of the surface of the semiconductor substrate, forming a conduction channel that is of the same conductivity type as the source and drain regions. As shown by curve A in FIG. 1, as the device size shrinks, the channel length decreases and, after some point, the threshold voltage starts to decrease appreciably with the channel length. The decrease of the threshold voltage with the channel length is theoretically predicted, and this phenomenon is known as the xe2x80x9cshort channel effect (SCE)xe2x80x9d.
Contrary to what is normally expected in modern technologies, it has been observed that a threshold voltage initially increases with decreasing channel length before the threshold voltage eventually decreases rather sharply, as shown by curve B in FIG. 1. This phenomenon has been termed xe2x80x9creverse short channel effect (RSCE)xe2x80x9d or xe2x80x9cthreshold voltage roll-offxe2x80x9d. Rafferty et al. (IEDM Tech. Dig., pp. 311, 1993) proposed that RSCE is a result of the transient enhanced diffusion of the channel profile induced by source/drain implantation. They explained that the damage caused by source/drain implantation generates silicon self-interstitials which flow outward and then recombine (annihilated) at the silicon surface under the gate oxide, thereby giving rise to a flux of the channel implant impurity toward the surface and raising the surface concentration of the channel impurity leading to RSCE. It has been experimentally discovered that RSCE can be avoided by preventing the channel implant from increasing at the surface of a silicon substrate.
Many approaches have been introduced, such as a retrograde channel profile, to control or even eliminate RSCE. As shown by curve B in FIG. 2, the retrograde channel profile has an impurity concentration peak deep under the surface., As disclosed in U.S. Pat. No. 5,565,377 issued to Weiner et al., a laser doping/annealing technique has been developed to achieve a desired retrograde impurity profile. According to Weiner et al., a retrograde impurity profile is formed by introducing dopants into a silicon substrate, i.e., by ion implanting dopants, and then exposing the silicon to multiple pulses of a high intensity energy source, e.g., laser. Such a pulsed energy source melts a portion of the silicon for a short time duration, and the molten silicon regrows at a high velocity from the bulk toward the surface due to the short total thermal cycle of the pulsed laser annealing, thereby forming a retrograde impurity profile with the impurity concentration peak of the dopant species at a certain depth below the surface of the silicon substrate. The method disclosed in Weiner et al. provides a relatively efficient way to tailor a desired retrograde profile by varying the process parameters, e.g., the amount of the impurity dopant, the number of times the substrate is melted and recrystallized, the rapidity of the recrystallization rate, duration of the pulsed energy, etc. However, although such conventional methodology provides a relatively simple way to form a retrograde channel profile by a laser technique, it is still difficult to achieve a desired retrograde impurity profile, i.e., a super steep retrograde profile as shown by curve C in FIG. 2, which maintains a relatively low concentration to a certain depth and then rapidly increasing toward a relatively flat impurity concentration peak.
Therefore, there exists a need for improved and production worthy methodology which provides more flexibility to tailor a desirable xe2x80x9csuper-steepxe2x80x9d retrograde channel profile.
An advantage of the present invention is an efficient, simplified and production worthy method of manufacturing a MOSFET device exhibiting reduced susceptibility to xe2x80x9creverse short channel effect (RSCE)xe2x80x9d.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following description or may be learned from the practice of the present invention. The objectives and advantages of the present invention maybe realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by forming a retrograde impurity implant of a first conductive type in a surface portion of a semiconductor substrate, wherein the retrograde impurity implant has an impurity concentration profile increasing from a main surface of the substrate to an impurity concentration peak at a first depth below the main surface of the substrate; laser annealing to melt a portion of the substrate and to flatten the impurity concentration peak of the retrograde impurity implant, thereby forming the retrograde impurity implant having a substantially flat impurity concentration peak at a second depth below the main surface of the substrate; and forming a semiconductor layer at a predetermined thickness on the main surface of substrate to controllably localize the flat impurity concentration peak at a predetermined depth below an upper surface of the semiconductor layer.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprising the steps of simultaneously laser doping and annealing a portion of a main surface of a semiconductor substrate to form a substantially flat impurity concentration peak below the main surface of the substrate; and forming a semiconductor layer at a predetermined thickness on the main surface of the substrate to controllably localize the substantially flat impurity concentration peak at a predetermined depth below an upper surface of the semiconductor layer.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustrating the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.